This invention relates to a method of testing an electronic circuit that has at least one flipflop with a master and a slave interconnected via a controllable coupling, wherein the method comprises quiescent current testing of the flipflop. The invention further relates to a circuit with such a flipflop.
A static flipflop is an important building block in the design of digital CMOS integrated circuits. A typical digital CMOS integrated circuit may contain several thousands of flipflops. A typical master-slave flipflop comprises a master latch and a slave latch interconnected through a transmission gate. Each respective one of the latches includes a respective further transmission gate to enable writing data and latching the data. In operational use of the flipflop the master and slave are alternately enabled to accept or store data by complementary control of the transmission gates, so as to functionally disconnect the flipflop""s input from its output.
Static flipflops such as those fabricated in CMOS, all share the same problem i.e. that particular bridging defects causing stuck-at faults cannot be detected through quiescent current measurements, also referred to as IDDQ-testing, without special provisions. Bridging defects are considered the single most important manufacturing defect mechanism responsible for yield loss. Special Design-for-Testability measures are required in order to enable detection of such defects in flipflops under IDDQ-testing. IDDQ-testing is recognized as the quality-improving complement to Boolean testing and among experts the opinion prevails that the quality achieved through IDDQ test techniques is not matched by any other test method.
European patent application 0 633 530 corresponding to U.S. application Ser. No. 08/271,801, incorporated herein by reference in its entirety. Teaches converting a sequential logic circuit into a combinatorial logic circuit. This conversion enables testing flipflop circuitry and scan chain circuitry using IDDQ test techniques in order to detect bridging defects and open defects. The flipflop""s capability of being reversibly convertible into a combinatorial logic circuit significantly reduces test complexity and substantially improves fault coverage. Basically, conversion to a combinatorial circuit renders the flipflop transparent. A logical conflict created across a defect is sustained by the data input of the flipflop. Making entire flipflop chains transparent drastically reduces test complexity.
In the test method discussed in aforesaid European patent application 0 633 530, master and slave are enabled simultaneously to render the logic combinatorial and, therefore, suitable for IDDQ-testing. Additional circuitry is required to enable this conversion to the transparent state. For example, the additional circuit provides independent control of the clock signal and its logic complement. This configuration requires dual clock lines to each flipflop, and therefore raises cost and affects timing criticality of the design as a proper timing relationship between the clock signal and its complement must be ensured throughout the entire circuit. Reference is made to the above European patent application 0 633 530 for further details and alternative ways to implement means for reversibly changing a sequential circuit to a combinatorial circuit.
It is, inter alia, an object of the invention to further reduce test complexity and cost. It is a further object to enable IDDQ-testing of flipflops while using less additional circuitry.
To this end, the invention provides a method of testing as specified in the preamble and characterized in that the method comprises applying the quiescent current testing to the flipflop whose controllable coupling is unidirectional, and in that the quiescent current testing comprises determining a quiescent current after clock-controlled data transfer from the master to the slave.
Specific low-resistive bridging defects in a master-slave flipflop cannot be detected by IDDQ-testing save by rendering the flipflop transparent according to the method cited in European patent application 0 633 530. This method, however, requires additional circuitry to effect the transparency. The invention is, among other things, based on the insight that rendering the flipflop or chains of flipflops transparent is not necessary if the coupling between master and slave is unidirectional.
The controllable coupling is conventionally implemented by a transmission gate. Such a bi-directional path between the master and slave, however, enables overwriting of the master, e.g., by a bridging defect in the slave, during data transfer from master to slave. The overwriting occurs as a consequence of a voltage conflict during this transitory phase and will go undetected in a quiescent state. The inventor has found that, if the controllable coupling between the master and slave is unidirectional at least during testing, the voltage conflict will persist without affecting the data of the master and will therefore be detectable by IDDQ-testing.
A flipflop having master and slave coupled through a buffer circuit is known from U.S. Pat. No. 5,189,315 issued to Akata. The buffer circuit blocks the master from undesirable influence of the slave and renders the flipflop suitable for higher clock rates than is achievable in un-buffered flipflops. This prior art reference, however, does not address the testability of such circuit, let alone the use of IDDQ-techniques. The present invention recognizes the fact that a flipflop with a unidirectional coupling between master and slave is highly suitable for being tested using a quiescent current method.
The unidirectional coupling may comprise a buffer circuit in series with a bi-directional switch. For example, the buffer circuit is a conventional CMOS-type inverter and the switch is a conventional transmission gate. Alternatively, the unidirectional coupling comprises a buffer with a first input connected to the master, an output connected to the slave and a control input for enabling the buffer. Proper enabling and disabling has the same function as controlling the transmission gate. A switched inverter can be used as such a buffer.
For the sake of completeness, reference is made to xe2x80x9cMetastability Behavior of CMOS ASIC Flip-Flops in Theory and Testxe2x80x9d, J. U. Horstmann et al., IEEE Journal of Solid Sate Circuits, Vol. 24, No. 1, February 1989, pp. 146-157, notably FIG. 13(b). This reference shows switched inverters used throughout a master-slave flipflop instead of the usual transmission gates in order to reduce metastability. A switched inverter is a conventional CMOS inverter connected between its supply terminals via complementarily clock-controlled transistors. Not only the coupling between the master and slave, but also the switches in the master and slave are comprised of such a switched inverter. In the invention, however, preferably only the coupling between the master and slave is unidirectional, the master and slave comprising a bi-directional switch each. Due to the switched inverters, the prior art design needs a greater number of additional transistors and clock control taps than does the circuit specified in the invention. Again, this prior art document does not address the issue of testability.
As demonstrated above, the inventor has recognized that the driving capability of the buffer in the unidirectional coupling plays a major role in the operation of the flipflop. The driving capability both sustains the quiescent current in case of a voltage conflict caused by a IDDQ-detectable defect, and enables overwriting the slave during normal operational use. Accordingly, the inventor has recognized that it is not the driving capability of the master which is relevant to testing and operational use, but the driving capability of the buffer. Therefore, the master""s inverters are better kept out of the signal path that runs between input and output of the flipflop, in order to reduce propagation delay in a flipflop with unidirectional coupling. In the flipflop of Akata referred to above, the signal path includes a master inverter, thus inflicting an extra, unnecessary propagation delay. According to the invention, the master comprises first and second inverters, the first inverter having an input connected to the unidirectional coupling and having an output connected to an input of the second inverter.